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| Ordering number : EN4466B CMOS LSI LC7527E Graphic Equalizer System Overview The LC7527E is a microprocessor controllable seven-band graphic equalizer LSI that does not require the use of external semiconductor inductors (simulated inductors). Package Dimensions unit: mm 3159-QFP64E [LC7527E] Functions * Left and right channel seven-band graphic equalizers * Each band operates in 2 dB steps. * Each band has a maximum boost of +12 dB and a maximum cut of -12 dB for a total of 13 settings. * Independent left and right channel operation * Serial data input supports CCB format communications with the system controller. * CMOS LSI with a 12 V breakdown voltage Features * This LSI, in conjunction with a control microprocessor, can implement in two chips, an electronic graphic equalizer with the following features. -- One touch gain control for each band -- One touch memory setting recall allows users to select desired frequency characteristics for each track. -- Since the LC7527E includes band filter amplifiers on chip, capacitors are the only external components required in application systems. -- Minimal switching noise due to the use of a Silicon gate CMOS process. * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. SANYO: QFP64E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN O3096HA(OT)/90894TH (OT) 4466-1/11 LC7527E Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Symbol VDD-VEE max VIN max1 Maximum input voltage VIN max2 VIN max3 Allowable power dissipation Operating temperature Storage temperature Note: * -6 V VEE VSS VDD Pd max Topr Tstg Conditions AVDD, AVEE, DVDD, DVEE* CL, DI, CE LIN1, LIN2, RIN1, RIN2 S1 Ta 85C Ratings 12 VSS - 0.3 to VDD + 0.3 VEE - 0.3 to VDD + 0.3 VEE - 0.3 to VDD + 0.3 280 -40 to +85 -50 to +125 Unit V V V V mW C C Allowable Operating Ranges at Ta = 25C, VSS = 0 V Parameter Symbol VDD Supply voltage VEE VDD-VEE Input high level voltage Input low level voltage Input amplitude voltage Clock pulse width Setup time Hold time Operating frequency VIH VIL VIN1 VIN2 toW tsetup tHOLD fopg AVDD, DVDD AVEE, DVEE AVDD, AVEE, DVDD, DVEE CL, DI, CE CL, DI, CE LIN1, LIN2, RIN1, RIN2 S1 CL CL, DI, CE CL, DI, CE CL 8.0 3.0 VSS VEE VEE 1 1 1 500 Conditions Ratings min typ 5 -5 11.0 VDD 1.0 VDD VDD max Unit V V V V V Vp-p V s s s kHz Electrical Characteristics at Ta = 25C, VDD = 5 V, VEE = -5 V, VSS = 0 V Parameter Symbol THD (1) THD (2) Total harmonic distortion THD (3) THD (4) Crosstalk Setting error Current drain Analog switch off leakage current CT B IDD IOFF Conditions VOUT = 1 Vrms, FLAT, f = 20 kHz VOUT = 1 Vrms, FLAT, f = 1 kHz VOUT = 300 mVrms, FLAT, f = 20 kHz with all bands at full boost VOUT = 300 mVrms, FLAT, f = 1 kHz with all bands at full boost VOUT = 1 Vrms, f = 20 kHz, FLAT, Rg = 1 k with other bands flat VDD-VEE = 11 V LIN1, LIN2, RIN1, RIN2 -2 Ratings min typ 0.01 0.001 0.042 0.045 58 +2 30 10 max 0.05 0.005 0.2 0.2 Unit % % % % dB dB mA A No. 4466-2/11 LC7527E Electrical Characteristics Test Circuit No. C1, C28 C2, C27 C3, C26 C4, C25 C5, C24 C6, C23 C7, C22 No. C29, C30, C31, C32 No. R1, R3, R4, R6 R2, R5 Unit (F) 10 Unit () 7.5 k 1M C8, C21 C9, C20 C10, C19 C11, C18 C12, C17 C13, C16 C14, C15 Unit (F) 0.94 0.034 0.377 0.0133 0.1506 5390 p 0.057 2156 p 0.0242 867 p 9200 p 3322 p 3770 p 1330 p Pin Assignment No. 4466-3/11 LC7527E Pin Functions Pin Lf1C1 Lf1C2 Lf1C3 Rf1C1 Rf1C2 Rf1C3 Lf2C1 Lf2C2 Lf2C3 Rf2C1 Rf2C2 Rf2C3 Lf3C1 Lf3C2 Lf3C3 Rf3C1 Rf3C2 Rf3C3 Lf4C1 Lf4C2 Lf4C3 Rf4C1 Rf4C2 Rf4C3 Lf5C1 Lf5C2 Lf5C3 Rf5C1 Rf5C2 Rf5C3 Lf6C1 Lf6C2 Lf6C3 Rf6C1 Rf6C2 Rf6C3 Lf7C1 Lf7C2 Lf7C3 Rf7C1 Rf7C2 Rf7C3 Pin No. 62 63 64 51 50 49 1 2 3 48 47 46 4 5 6 45 44 43 7 8 9 42 41 40 10 11 12 39 38 37 13 14 15 36 35 34 17 18 19 32 31 30 Circuit type Function Left channel f1 band control block External capacitor connections Right channel f1 band control block External capacitor connections Left channel f2 band control block External capacitor connections Right channel f2 band control block External capacitor connections Left channel f3 band control block External capacitor connections Right channel f3 band control block External capacitor connections Left channel f4 band control block External capacitor connections Right channel f4 band control block External capacitor connections Left channel f5 band control block External capacitor connections Right channel f5 band control block External capacitor connections Left channel f6 band control block External capacitor connections Right channel f6 band control block External capacitor connections Left channel f7 band control block External capacitor connections Right channel f7 band control block External capacitor connections AVDD AVEE DVDD DVEE VSS 23 56 22 57 28 Power supply: +5 V typ. Audio signal power supply Power supply: -5 V typ. Audio signal power supply Power supply: +5 V typ. Logic signal power supply Power supply: -5 V typ. Logic signal power supply Power supply: 0 V AVDD must be equal to DVDD, and AVEE must be equal to DVEE. Continued on next page. No. 4466-4/11 LC7527E Continued from preceding page. Pin Pin No. Circuit type Function LVref RVref 58 55 Power supply: Analog ground The impedance of the pattern connected to these pins should be kept as low as possible. LVref and RVref are not connected to the VSS pin. LIN1 LIN2 59 60 Left channel audio signal input IN1 is normally connected to an operational amplifier inverting input. IN2 is normally connected to an operational amplifier noninverting input. Right channel audio signal input IN1 is normally connected to an operational amplifier inverting input. IN2 is normally connected to an operational amplifier noninverting input. RIN1 RIN2 54 53 CE 27 Chip enable input. Internal data is latched when this pin goes from high to low and the analog switches operate. Data transfers are enabled when this pin is high. CL DI 25 26 Clock input. Schmitt inverter input circuit Data input. Schmitt inverter input circuit S1 24 Dual chip system chip select input. By connecting S1 (this pin) to either VDD or VEE, data input is enabled when the address matches the corresponding address listed below. S1 = VDD Address: 8C S1 = VEE Address: 8D NC NC NC NC NC NC NC 16 20 21 29 33 52 61 No connection. Do not connect signals to these pins. No. 4466-5/11 LC7527E Equivalent Circuit Internal Equivalent Circuit (for a single band) No. 4466-6/11 LC7527E Data Input The LC7527E is controlled by inputting stipulated data using the CE, CL, and DI pins. The data has a total of 20 bits, of which eight are address and 12 are data. No. 4466-7/11 LC7527E Sample Application Circuit Unit (resistance: , capacitance: F) Note: If at all possible, use bipolar capacitors for all capacitors that do not have a polarity specified. *1. A resistor of about 100 k is recommended if impulse noise (popping sounds) is a problem. No. 4466-8/11 LC7527E External Component Value Calculations The external capacitors required for each band in the LC7527E are the structural elements in semiconductor inductors (simulated inductors). The remainder of this section presents the equivalent circuits and the formulas used to determine the center frequencies. 1. Semiconductor Inductor Equivalent Circuit The LC7527E provides circuits with differing constants for the low and high bands. 2. Calculation Example Specifications: 1) Center frequency: Fo = 63 Hz 2) Q at maximum boost: Q+12 dB = 1.05 * Derive the sharpness Qo of the semiconductor inductor itself. (R1 + R4) Qo = x Q+12 dB 4.064 See the internal equivalent circuit figure for R4. R1 * Derive C1. C1 = 1/2FoR1Qo 0.953 (F) * Derive C2. C2 = Qo/2FoR2 0.034 (F) 3. Sample Values for C1 and C2 Center frequency Fo (Hz) 63 160 400 1000 2500 6300 16000 C1 (F) 0.953 0.377 0.151 0.060 0.024 9563 p 3765 p C2 (F) 0.034 0.014 5390 p 2156 p 862 p 3422 p 1348 p No. 4466-9/11 LC7527E No. 4466-10/11 LC7527E Usage Notes 1. The states of the internal analog switches are undefined when power is first applied. System output should be muted until control data has been sent to the LC7527E. 2. To prevent the high frequency digital signals associated with data transfers over the CL, CI, and DI pins from generating interference in the analog signals, either guard those lines with a ground pattern or use shielded cables. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1996. Specifications and information herein are subject to change without notice. No. 4466-11/11 |
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